The present invention generally relates to a method for packaging integrate circuit chips and packages formed and more particularly, relates to a method for packaging back-to-back dual-chip packages utilizing both lead frame bonding and solder ball bonding techniques and packages formed.
In recent years, ball grid array (BGA) packages for semiconductor chips have been used extensively in the semiconductor industry. BGA packages utilize solder balls for establishing electrical interconnections between a chip and a printed circuit board (PCB) and provide high quality and reliability. It has been commonly used in CPU chips in personal computers, in chips of multichip modules and in other high I/O chips.
A BGA package can be made more compact in size than other packages, for instance, than a plastic quad flat package (PQFP). A BGA package which has an IC chip wire bonded to a substrate can be easily soldered to a printed circuit board by solder balls which are arranged in an area array. Other benefits can also be achieved by the BGA package. For instance, there are fewer soldering defects in a BGA assembly when compared to the PQFPs and the self-alignment effect of the solder balls. As a result, minor misalignments in the mounting position can be automatically corrected by the surface tension of the molten solder during a reflow process.
The BGA package utilizes an area array external electrodes which are normally formed of lead/tin solder balls. The solder balls are placed on a back surface of the package at spacings between about 1 mm and about 1.5 mm. The BGA package further provides the benefits of higher external pin-count density, larger thermal paths to the package surroundings and improved pre-testability.
A typical BGA package 10 is shown in FIG. 1A in an enlarged, cross-sectional view. The package 10 is constructed by first bonding an IC die 12 to a substrate 14 by an adhesive layer 28 and then making electrical connections between the two by wire bonds 16. The IC die 12 is typically interconnected to a plastic resin molded substrate 14 in a transfer molding process. Solder balls 20 are then attached to the backside 18 of the substrate 14 in a post-molding operation. A plastic molding compound or encapsulant 24 is utilized in the transfer molding process to encapsulate the IC die 12 and the bonding wires 16 with a top surface 22 of the substrate. Inside the substrates 14 and 18, is a double-sided printed wiring board (PWB) 30 which has copper laminated to both sides of an insulating plastic material. Via holes 26 are drilled and filled with a conductive metal, i.e., electroless copper, followed by a platform plating process. In more sophisticated BGA package structures, multi-layer substrates which have broader power planes or ground planes, or both are utilized for low inductance and larger thermal-path connections.
Solder balls 20 may be formed on the bottom side 18 of the double-sided PWB 30 by a variety of techniques which include solder-ball attachment and solder-paste screen printing. After the solder balls are formed, a reflow operation usually follows to complete the metallurgical connections.
The BGA package 10 shown in FIG. 1A is formed by a conventional chip scale package technique utilizing wire bonding and plastic encapsulation. The IC chip is mounted in a face-up position with the aluminum bonding pads 32 facing upwardly. In such a position, not only the bonding wires 16 leading from the aluminum bonding pads 32 to the upper copper lead 34 in the PWB 30 need to be excessively long, but also the problem of wire sweep may occur during the plastic molding process. The wire sweep problem causes wire breakage or otherwise defective wire bonds.
In a more recently developed BGA package 40, also known as a micro-BGA package shown in FIG. 1B, an IC chip 42 is first bonded to a TAB (tape automated bonding) tape 44 through lead fingers 46 and gold coated copper interconnects 48. After TAB bonding, solder balls 52 are formed on the TAB tape 44 for making connections with the lead fingers 46 and subsequently with the IC chip 42. The handling of the flexible TAB tape 44 and the lead fingers 46 is problematic and frequently cause processing difficulties. In the final stage of the process, a liquid epoxy molding compound 54 and an elastomeric compound 56 are sequentially injected into a mold in which the chip 42 and the tape 44 are positioned to encapsulate the package 40. In the micro-BGA structure 40, the fabrication process is complicated since the alignment between the IC chip 42, the lead fingers 46 and the TAB tape 44 must be precisely controlled, the packaging process can only be carried out at a high cost.
Attempts have been made by others to bond two IC chips arranged in a face-to-face relationship to a single site of finger leads situated in a tape lead frame. This is shown in FIG. 1C. The finger leads contained at the single site in the lead frame are divided into two groups which are bonded to two IC chips in two separate bonding processes. The first group has its inner free ends configured to contact bumps on a first chip, while the second group of finger leads are configured outside the periphery of the first chip after it is bonded to the tape. As shown in FIG. 1C, a first IC chip 36 is first bonded to a plurality of long finger leads 38 by solder bumps 58. A second IC chip 50 is then bonded to a plurality of short finger leads (not shown) by solder bumps 60. The completed assembly, which includes the fist IC chip 36 and the second IC chip 50 is then encapsulated in an insulating material 62 to protect the structure. The method, eventhough allowing a higher package density requires complicated lead frame formation and a two-step lead finger bonding process.
It is therefore an object of the present invention to provide a method for forming a dual-chip package that does not have the drawbacks or shortcomings of the conventional dual-chip packages.
It is another object of the present invention to provide a method for forming a dual-chip package wherein two IC chips are arranged in a back-to-back configuration.
It is a further object of the present invention to provide a back-to-back dual-chip package that combines the benefits of a BGA process and a lead frame bonding process in a single package.
It is another further object of the present invention to provide a back-to-back dual-chip package for memory devices by utilizing existing memory chip design and fabrication equipment.
It is still another object of the present invention to provide a method for forming a back-to-back dual-chip package wherein a first chip is connected to the outside circuit by lead fingers and a second chip is connected to the outside circuit by solder balls.
It is yet another object of the present invention to provide a method for forming a back-to-back dual-chip package and encapsulating the package in an insulating plastic.
It is still another further object of the present invention to provide a method for forming a back-to-back dual-chip package wherein both solder balls and lead fingers are used for connection to outside circuits on a printed circuit board.
It is yet another further object of the present invention to provide a back-to-back dual-chip package which includes a plurality of finger leads for a first chip and a plurality of solder balls for a second chip for connecting to outside circuits.
In accordance with the present invention, a method for forming a back-to-back dual-chip package and devices formed by the method are provided.
In a preferred embodiment, a method for forming a back-to-back dual-chip package can be carried out by the operating steps of providing a first IC chip which has a first plurality of conductive elements formed on a top surface, planting a first plurality of solder balls on the first plurality of conductive elements on the first IC chip, providing a lead frame which has a first plurality of lead fingers emanating therefrom, bonding the first plurality of solder balls to free ends of the first plurality of lead fingers, providing a second IC chip which has a second plurality of conductive elements formed on a top surface, planting a second plurality of solder balls on the second plurality of conductive elements, bonding a bottom surface of the first IC chip to a bottom surface of the second IC chip by adhesive means, and encapsulating the first and second IC chips in an insulating material with the first IC chip facing upwardly and the second IC chip facing downwardly such that the first plurality of solder balls and the free ends of the first plurality of lead fingers are substantially covered by the insulating material while the second plurality of solder balls are substantially exposed.
The method for forming a back-to-back dual-chip package may further include the step of providing a first IC chip which has a first plurality of bond pads or copper traces formed on a top surface, the step of planting a first plurality of solder balls on the first plurality of conductive elements by a screen printing technique or an electroless plating technique, or the step of bonding the first plurality of solder balls to free ends of the first plurality of lead fingers which are coated with a solder material. The method may further include the step of providing a second IC chip which has a total planar area that is substantially similar to the total planar area of the first IC chip. The method may further include the step of planting a second plurality of solder balls on the second plurality of conductive elements by a screen printing or an electroless plating technique.
In the method, the first plurality and the second plurality of solder balls may be formed of a solder material containing Pb and Sn. The adhesive means may be a thermally conductive adhesive that contains metal particles. The adhesive means may be an epoxy-based adhesive. The adhesive means may also be a thermoset polymeric material. The insulating material used to encapsulate the first and second IC chips is a thermoset polymeric material. The method may further include the step of connecting the second plurality of solder balls to a printed circuit board. The opposite ends of the first plurality of lead fingers may be exposed outside the insulating material after the encapsulating step. The opposite ends of the first plurality of lead fingers may be exposed outside the insulating material and formed for connecting to a printed circuit board.
The present invention is further directed to a back-to-back dual-chip package which includes a first IC chip that has a first plurality of conductive elements formed on a top surface, a first plurality of solder balls on the first plurality of conductive elements, a lead frame which has a first plurality of lead fingers emanating therefrom, a first plurality of free ends of the first plurality of lead fingers bonded to the first plurality of solder balls, a second IC chip which has a second plurality of conductive element formed on a top surface, a second plurality of solder balls on the second plurality of conductive elements, an adhesive layer bonding a bottom surface of the first IC chip to a bottom surface of the second IC chip, and an encapsulating compound covering the first and second IC chips with the first chip facing upwardly and the second chip facing downwardly, while the second plurality of solder balls are substantially exposed.
In the back-to-back dual-chip package, the first and the second plurality of conductive elements may be formed of bond pads or copper traces. The free ends of the first plurality of lead fingers may be covered with a solder material prior to bonding with the first plurality of solder balls. The first IC chip and the second IC chip may have substantially the same planar area. The first plurality and the second plurality of solder balls may be formed of a material containing Pb/Sn.
In the back-to-back dual-chip package, the adhesive means for bonding the first chip to the second chip may be a thermally conductive adhesive. The adhesive means may also be an epoxy-based material. The insulating material for encapsulating the first and second IC chips may be a thermoset-based polymeric material. The opposite ends of the first plurality of lead fingers maybe exposed outside the insulating material. The opposite ends of the first plurality of lead fingers may be exposed outside the insulating material and formed for connecting to a printed circuit board. The dual-chip package may further include a printed circuit board which is connected to the second plurality of solder balls on the second IC chip.